Intermetal dielectric layers are commonly used to isolate conductive structures, such as metal layers, from subsequently deposited conducting layers. FIG. 1 shows a cross-sectional area of a semiconductor substrate 100. Atop the substrate is a plug 102 in an interlayer dielectric 104, a conductive structure 106 above the plug 102, and an intermetal dielectric layer 108. In a conventional method for forming the structure shown in FIG. 1, the metal layer forming the conductive structure 106 is overetched. Overetching of the metal layer is performed to ensure removal of metal residue. However, this overetching also causes a removal of a portion of the interlayer dielectric 104, undesirably causing an increase in step height. The increased step height worsens the planarization of the subsequent intermetal dielectric 108. In addition, the increased step height presents a keyhole problem. That is, voids 110 are created during the deposition of the intermetal dielectric layer 108.
What is needed is a method for forming a planar intermetal dielectric layer that eliminates the aforementioned problems.